Chip package and method for forming the same

ABSTRACT

A chip package includes a substrate having an upper surface and a lower surface, a plurality of conducting pads located under the lower surface of the substrate, and a dielectric layer located between the conducting pads. A hole is provided in the substrate, which extends from the upper surface towards the lower surface of the substrate. A sidewall or a bottom of the hole exposes a portion of the conducting pads. The upper opening of the hole near the upper surface is smaller than a lower opening of the hole near the lower surface. An upper conducting pad has at least an opening or a trench exposing a lower conducting pad of the conducting pads. A conducting layer is disposed in the hole, which electrically contacting at least one of the conducting pads.

CROSS REFERENCE

This Application is a Continuation of U.S. application Ser. No. 13/044,457, filed on Mar. 9, 2011 and entitled “CHIP PACKAGE AND METHOD FOR FORMING THE SAME”, which claims the benefit of U.S. Provisional Application No. 61/313,087, filed on Mar. 11, 2010, and the benefit of U.S. Provisional Application No. 61/315,850, filed on Mar. 19, 2010, the entirety of which are incorporated by reference herein.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a chip package, and in particular relates to a chip package having a through-substrate via (through-substrate via, TSV).

2. Description of the Related Art

Recently, through-substrate vias are frequently being formed in a chip packages to accommodate miniaturization and multi-functionality requirements of chips. In order to further improve the functionality of the chip, conducting routes to the through-substrate vias need to be improved, such that high density conducting routes may be achieved even if the size of the chip package continues to shrink. In addition, it is desired to improve the structural reliability of the through-substrate via.

BRIEF SUMMARY OF THE INVENTION

According to an embodiment of the invention, a chip package is provided. The chip package includes a substrate having an upper surface and a lower surface, a plurality of conducting pads located in the substrate or under the lower surface, a dielectric layer located between the conducting pads, a hole extending from the upper surface towards the lower surface of the substrate and exposing a portion of the conducting pads, and a conducting layer located in the hole and electrically contacting the conducting pads.

According to an embodiment of the invention, a method for forming a chip package is provided. The method comprises: providing a substrate having an upper surface and a lower surface, wherein the substrate comprises: a plurality of conducting pads located in the substrate or below the lower surface of the substrate; and a dielectric layer located between the conducting pads; forming a hole in the substrate, wherein the hole extends from the upper surface towards the lower surface, and the hole exposes a portion of the conducting pads; and forming a conducting layer in the hole, wherein the conducting layer is electrically connected to the conducting pads.

According to an embodiment of the invention, a chip package is provided. The chip package comprises: a carrier substrate; a chip substrate having a front surface and a back surface, wherein the front surface of the chip substrate is bonded on the carrier substrate to form a bonding surface; a plurality of conducting pads located on the front surface of the chip substrate, wherein at least one conducting pad has a window; a dielectric layer located between the conducting pads; a through-hole located in the carrier substrate and penetrating through the bonding surface and the window to expose one conducting pad or multiple conducting pads of the conducting pads; and a conducting layer located in the through hole and electrically connected to the one conducting pad or the multiple conducting pads.

According to an embodiment of the invention, a method for forming a chip package is provided. The method includes: providing a carrier substrate; providing a chip substrate having a front surface and a back surface, wherein the front surface of the chip substrate is bonded on the carrier substrate to form a bonding surface, the front surface of the chip substrate comprises at least one conducting pad, and the at least one the conducting pad has an insulating window and a dielectric layer covering the at least one conducting pad; forming a through-hole in the carrier substrate to penetrate through the bonding surface and the insulating window to expose one conducting pad or multiple conducting pad of the at least one conducting pad; and forming a conducting layer in the through-hole to electrically contact with one conducting pad or multiple conducting pads of the at least one conducting pad.

According to an embodiment of the invention, a method for forming a chip package is provided. The method includes: providing a carrier substrate; providing a chip substrate a chip substrate having a front surface and a back surface, wherein the front surface of the chip substrate is bonded on the carrier substrate to form a bonding surface, the front surface of the chip substrate comprises at least one conducting pad, and the at least one the conducting pad has an insulating window and a dielectric layer covering the at least one conducting pad; forming a through-hole extending from a surface of the carrier substrate and penetrating through the bonding surface and the insulating window to expose one conducting pad or multiple conducting pads of the at least one conducting pad; and forming a conducting layer in the through-hole to electrically contact with one conducting pad or multiple conducting pads of the at least one conducting pad, wherein the insulating window is formed before the chip substrate and the carrier substrate are bonded or before the through-hole is formed.

A detailed description is given in the following embodiments with reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:

FIGS. 1A-1C are cross-sectional views showing the steps of forming a chip package according to an embodiment of the present invention;

FIGS. 2A-2C are enlarged cross-sectional views showing the steps of forming a chip package according to an embodiment of the present invention;

FIGS. 3A-3C are enlarged cross-sectional views showing the steps of forming a chip package according to an embodiment of the present invention;

FIGS. 4A-4B are enlarged cross-sectional views showing the steps of forming a chip package according to an embodiment of the present invention;

FIG. 5 is an enlarged cross-sectional view partially showing a chip package according to an embodiment of the present invention;

FIGS. 6A-6E are top views partially showing chip packages according to embodiments of the present invention;

FIG. 7 is a cross-sectional view showing a chip package according to an embodiment of the present invention;

FIGS. 8-13 are cross-sectional views showing the steps of forming a chip package according to an embodiment of the present invention;

FIGS. 14A-14B are cross-sectional views showing the steps of forming a chip package according to another embodiment of the present invention;

FIGS. 15A-15C are enlarged cross-sectional views showing the steps of forming a chip package according to an embodiment of the present invention;

FIGS. 16A-16C are enlarged cross-sectional views showing the steps of forming a chip package according to an embodiment of the present invention; and

FIGS. 17A-17C are cross-sectional views showing the steps of forming a chip package according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.

It is understood, that the following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. Note that the present disclosure may repeat reference numbers and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Furthermore, descriptions of a first layer “on,” “overlying,” (and like descriptions) a second layer include embodiments where the first and second layers are in direct contact and those where one or more layers are interposing the first and second layers.

A chip package according to an embodiment of the present invention may be applied to active or passive devices, or electronic components with digital or analog circuits, such as opto electronic devices, micro electro mechanical systems (MEMS), micro fluidic systems, and physical sensors for detecting heat, light, or pressure. Particularly, a wafer scale package (WSP) process may be applied to package semiconductor chips, such as image sensor devices, light-emitting diodes (LEDs), solar cells, RF circuits, accelerators, gyroscopes, micro actuators, surface acoustic wave devices, pressure sensors, ink printer heads, or power modules.

The wafer scale package process mentioned above mainly means that after the package process is accomplished during the wafer stage, the wafer with chips is cut to obtain separate independent packages. However, in a specific embodiment, separate independent chips may be redistributed overlying a supporting wafer and then be packaged, which may also be referred to as a wafer scale package process. Note that the above mentioned wafer scale package process may also be adapted to form chip packages of multi-layer integrated circuit devices by stacking a plurality of wafers having integrated circuits.

In a chip package according to embodiments of the invention, each pattern of the multi-layered conducting pads is designed such that a through-substrate conducting structure formed in the package may electrically contact with the multi-layered conducting pads, improving the structural reliability of the chip package and increasing conducting routes connected to the through-substrate conducting structure.

FIGS. 1A-1C are cross-sectional views showing the steps of forming a chip package according to an embodiment of the present invention. As shown in FIG. 1A, a substrate is provided, which includes an upper surface 100 a and a lower surface 100 b. The substrate 100 may include, for example, a semiconductor material or a ceramic material. In one embodiment, the substrate 100 may be a semiconductor wafer (such as a silicon wafer) which benefits performing of a wafer-level package process. Adopting a wafer-level package process to form a chip package may reduce fabrication cost and time.

In one embodiment, the substrate 100 includes a conducting pad structure 110 which is located under the lower surface 100 b of the substrate 100. However, in another embodiment, the conducting pad structure 110 may be located in the substrate 100. The conducting pad structure 110 is a stacked structure of a plurality of conducting pads, such as a plurality of conducting pads having dielectric layers interposed therebetween. The structure of the conducting pad structure 110 will be illustrated in detail with references made to FIGS. 2A-2C which are enlarged cross-sectional views showing the steps of forming a chip package according to an embodiment of the invention. In the embodiment shown in FIG. 1A, the conducting pad structure 110 is located below the lower surface 100 b of the substrate 100 and separated from the lower surface 100 b of the substrate 100 by an insulating layer 102. In addition, a substrate 106 may be disposed under the substrate 100 and the conducting pad structure 110. The substrate 106 may include, for example, an insulating material. In one embodiment, the substrate 106 may be a spacer layer disposed on a glass substrate.

Referring to FIG. 2A, an enlarged cross-sectional view showing the area A of the embodiment in FIG. 1A is illustrated. A conducting pad 110 b, a dielectric layer 113, a conducting pad 110 a, and the insulating layer 102 are formed on the substrate 106. In one embodiment, a pattern of the conducting pad 110 a is designed such that a portion of the conducting pad 110 b thereunder is exposed. In one embodiment, the conducting pad 110 a has at least an opening (or a trench) 602. The opening 602 exposes the dielectric layer 113 and the conducting pad 110 b directly below the opening. That is, in this embodiment, an upper conducting pad (110 a) has at least an opening (or a trench) which exposes a lower conducting pad (110 b). It should be appreciated that “exposed” herein does not mean that the conducting pad 110 can be seen and means that the opening 602 overlaps with a portion of the conducting pad 110 b directly below the opening.

Next, a hole is formed in the substrate 100. The hole extends from the upper surface 100 a towards the lower surface 100 b of the substrate 100, and the hole exposes a portion of the conducting pad 110 a and a portion of the conducting pad 110 b. In one embodiment, the hole is formed in a single etching process. In another embodiment, the hole is stepwise formed. Hereafter, examples are provided to illustrate the procedure of stepwise forming the hole exposing a portion of the conducting pad 110 a and a portion of the conducting pad 110 b.

For example, referring to FIG. 1A, in this embodiment, a first hole 108 is formed from the upper surface 100 a of the substrate 100. The first hole 108 extends towards the conducting pad structure 110 (i.e., extends towards the conducting pad 110 a). Take the embodiment of FIG. 1A as an example, the first hole 108 penetrates the substrate 100 and stops at the insulating layer 102 between the substrate 100 and the conducting pad structure 110. Then, an insulating layer 104 may be optionally formed on a sidewall and a bottom of the first hole 108 to electrically isolate the substrate 100 and a conducting layer, which is subsequently formed in the hole.

Next, as shown in FIG. 1B, a second hole 112 is formed from the bottom of the first hole 108. That is, portions of the insulating layers 104 and 102 are removed such that the conducting pad structure 110 thereunder is exposed. Note that the second hole 112 further exposes the conducting pads 110 a and 110 b. Referring to FIG. 2B, an enlarged cross-sectional view showing the area A of the embodiment of FIG. 1B is illustrated.

As shown in FIGS. 2A and 2B, the formation step of the second hole 112 includes removing the insulating layer 102 in the opening 602 of the conducting pad 110 a and a portion of the dielectric layer 113 thereunder. In one embodiment, a sidewall of the formed second hole 112 exposes a portion of the conducting pad 110 a. For example, a side of the conducting pad 110 a is exposed, as shown in FIG. 2B. In one embodiment, a bottom of the formed second hole 112 exposes a portion of the conducting pad 110 b. For example, an upper surface of the conducting pad 110 b is exposed, as shown in FIG. 2B. Because only an insulating material is removed during the formation of the hole 112, the hole may be formed in a single etching process. Note that the etching rate of the chosen etchant for the dielectric material or insulating material is preferably higher than that for the metal material or conducting material.

As mentioned above, the pattern of the conducting pad 110 a is designed to expose a portion of the conducting pad 110 b thereunder. Thus, during the formation of the second hole 112, the materials which are removed are substantially the insulating material in the opening 602 of the conducting pad 110 a and the dielectric material thereunder. The second hole 112 may be therefore formed in a single etching process.

FIG. 6A is a top view partially showing a chip package according to an embodiment of the present invention, which merely shows a relationship between the conducting pads 110 a and 110 b. It should be appreciated that the top view shown in FIG. 6A is only used to illustrate a specific example, but not used to limit embodiments of the present invention. As shown in FIG. 6A, the conducting pad 110 a has at least an opening 602 which exposes the conducting pad 110 b thereunder. That is, the conducting pads 110 a and 110 b with different depths are exposed in the second hole 112.

Next, referring to FIG. 1C, a conducting layer 114 is formed in a hole formed by the first hole 108 and the second hole 112. Referring to FIG. 2C, an enlarged cross-sectional view showing the area A of the embodiment in FIG. 1C is illustrated. As shown in FIG. 2C, the conducting layer 114 extends into the second hole 112 and electrically contacts with the conducting pad 110 a and the conducting pad 110 b. In one embodiment, the conducting layer 114 may be fixed in the second hole 112 for a better structural stability. The conducting layer 114 simultaneously contacts with the conducting pad 110 a and the conducting pad 110 b such that the conducting layer 114 may be connected to more conducting routes. In one embodiment, the conducting pad 110 a and the conducting pad 110 b are connected to a same electronic device. Because the conducting layer 114 simultaneously and electrically contacts with the conducting pad 110 a and the conducting pad 110 b, a short of the conducting routes connected to the electronic device may be ensured from occurring. In another embodiment, the conducting pad 110 a and the conducting pad 110 b are connected to different electronic devices, respectively. The different electronic devices may transmit or receive electrical signals through the conducting layer 114 and the conducting pad 110 a and the conducting pad 110 b, respectively.

The conducting pad structure 110 according to embodiments of the invention includes not only two conducting pads (110 a, 110 b), but may further include another conducting pad. FIGS. 3A-3C are enlarged cross-sectional views showing the steps of forming a chip package according to another embodiment of the present invention, wherein same or similar reference numbers are used to designate same or similar elements. Note that because the main difference between the embodiment shown in FIG. 3 and the embodiment shown in FIG. 2 is the design of the conducting pad structure 110, reference may be made to the descriptions corresponding to FIGS. 1A-1C concerning the fabrication method of the embodiment shown in FIG. 3. Thus, repeated descriptions are not provided.

As shown in FIG. 3A, in one embodiment, the chip package includes the conducting pad 110 a and the conducting pad 110 b and further includes a conducting pad 110 c which is located in a dielectric layer between the conducting pads 110 a and 110 b. As shown in FIG. 3A, the conducting pad 110 b, a dielectric layer 113 a, the conducting pad 110 c, a dielectric layer 113 b, the conducting pad 110 a, and the insulating layer 102 are formed on the substrate 106. In one embodiment, a pattern of the conducting pad 110 a is designed to expose a portion of the conducting pad 110 c thereunder and a portion of the conducting pad 110 b. In one embodiment, the conducting pad 110 a has at least an opening (or a trench) 602. The opening 602 exposes the dielectric layer 113 b, the conducting pad 110 c thereunder, the dielectric layer 113 a, and the conducting pad 110 b thereunder. In addition, a pattern of the conducting pad 110 c is also designed to have at least an opening (or a trench). The opening 604 exposes the dielectric layer 113 a and the conducting pad 110 b thereunder.

In other words, a chip package according to an embodiment of the present invention includes a plurality of conducting pads (such as the conducting pads 110 a, 110 c, 110 b), wherein an upper conducting pad of the conducting pads has at least an opening or a trench exposing a lower conducting pad of the conducting pads. For example, the conducting pad 110 a (the upper conducting pad) has the opening 602 exposing the conducting pads 110 c and 110 b (the lower conducting pads). Similarly, the conducting pad 110 c (the upper conducting pad) has the opening 604 exposing the conducting pad 110 b (the lower conducting pad).

Then, a hole is formed in the substrate 100. The hole extends from the upper surface 100 a towards the lower surface 100 b of the substrate 100. The hole exposes a portion of the conducting pad 110 a, a portion of the conducting pad 110 c, and a portion of the conducting pad 110 c. In one embodiment, the hole is formed in a single etching process. In another embodiment, the hole is stepwise formed.

Similarly, in this embodiment, the first hole 108 may also be first formed (as shown in FIG. 1A), and the second hole 112 is then formed at the bottom of the first hole 108, as shown in FIG. 1B. FIG. 3B are an enlarged cross-sectional view showing the structure near the second hole 112.

Similarly, during the formation of the second hole 112, the material which is removed is substantially the insulating material in the opening 602 and the dielectric material thereunder. Thus, the second hole 112 may be formed in a single etching process.

FIG. 6B is a top view partially showing a chip package according to an embodiment of the present invention, which merely shows a relationship between the conducting pads 110 a, 110 b, and 110 c. It should be appreciated that the top view shown in FIG. 6B is only used to illustrate a specific example, but not used to limit embodiments of the present invention. As shown in FIG. 6B, the conducting pad 110 a has at least an opening 602 which exposes the conducting pads 110 c and 110 b thereunder. In addition, the conducting pad 110 c has at least an opening 604 which exposes the conducting pad 110 b thereunder. That is, the conducting pads 110 a, 110 c, and 110 b with different depths are exposed in the second hole 112.

Similarly, as shown in FIG. 3C, the conducting layer 114 is then formed, which extends into the second hole 112 to electrically contact with the conducting pads 110 a, 110 c, and 110 b. In one embodiment, the conducting layer 114 may be fixed in the second hole 112 for a better structural stability. The conducting layer 114 simultaneously contacts with the conducting pads 110 a, 110 c, and 110 b, which may be connected to more conducting routes.

As mentioned above, through the design of the pattern of the conducting pad, a hole simultaneously exposing a plurality of conducting pads may be formed in a single etching process, increasing the number of conducting routes which are electrically connected to by the conducting layer to be formed in the hole (the through substrate conducting structure). Note that because the surface profile of the formed hole is relatively rough (because of the plurality of conducting pads with different depths), the adhesion between the conducting layer and the sidewall of the hole may be improved, thus increasing the structural stability of the through substrate conducting structure.

It should be appreciated that the design of the pattern of the conducting pad may have a variety of types and is not limited to those shown in FIGS. 6A-6B. FIGS. 6C-6E are top views partially showing chip packages according to embodiments of the present invention. Similarly, FIGS. 6C-6E are only used to illustrate examples, but not used to limit embodiments of the present invention.

As shown in FIG. 6C, in one embodiment, the conducting pad 110 a has a rectangular opening 602 which exposes the conducting pads 110 c and 110 b thereunder. The conducting pad 110 c has a plurality of rectangular openings 604 which expose the conducting pad 110 b thereunder.

As shown in FIG. 6D, in another embodiment, the conducting pad 110 a has a rectangular opening 602 which exposes the conducting pads 110 c and 110 b thereunder. The conducting pad 110 c has a plurality of rectangular openings 604 (or trenches) which expose the conducting pad 110 b thereunder.

As shown in FIG. 6E, in yet another embodiment, the conducting pad 110 a has a rectangular opening 602 which exposes the conducting pads 110 c and 110 b thereunder. The conducting pad 110 c has a plurality of openings 604 including square openings and rectangular openings (or trenches) which expose the conducting pad 110 b thereunder. As mentioned above, the shapes, numbers, and distributions of the openings of the conducting pad may be adjusted according to requirements.

FIGS. 4A-4B are enlarged cross-sectional views showing the steps of forming a chip package according to an embodiment of the present invention, wherein same or similar reference numbers are used to designate same or similar elements, and the structure shown in FIG. 4A is similar to that shown in FIG. 3A, and the main difference is shown in FIG. 4B.

As mentioned above, the formation of the second hole 112 includes using a single etching process. In one situation, during the etching process to form the second hole 112, the conducting pad beside the hole may be partially removed. As shown in FIG. 4B, portions of the conducting pads 110 a and 110 c may also be etched and removed during the formation of the second hole 112. In this situation, the thickness of the portion of the conducting pad 110 a near the hole 112 increases along a direction away from the hole 112. Similarly, in one embodiment, the thickness of the portion of the conducting pad 110 c near the hole 112 increases along a direction away from the hole 112. When the conducting layer 114 is subsequently formed in the second hole 112, the conducting layer 114 may still electrically contact with the conducting pads 110 a, 110 c, and 110 b. Note that because portions of the conducting pads 110 a and 110 c are removed, the contact area between the conducting layer 114 and the conducting pads 110 a and 110 c is therefore increased, as shown in FIG. 4B.

FIG. 5 is an enlarged cross-sectional view partially showing a chip package according to an embodiment of the present invention. Similarly, in this embodiment, portions of the conducting pads 110 a and 110 b are removed during the formation of the second hole 112. In this situation, the thickness of the portion of the conducting pad 110 a near the hole 112 increases along a direction away from the hole 112. Similarly, the thickness of the portion of the conducting pad 110 b near the hole 112 increases along a direction away from the hole 112. In addition, in this embodiment, the conducting pad 110 b is designed to have an opening 605 which exposes the substrate 106 thereunder. In one embodiment, the second hole 112 may further extend into the substrate 106. For example, in one embodiment, the second hole 112 may extend into a spacer layer of the substrate 106.

FIG. 7 is a cross-sectional view showing a chip package according to an embodiment of the present invention, wherein same or similar reference numbers are used to designate same or similar elements. In this embodiment, the chip package further includes a trench 702 which extends from the upper surface 100 a towards the lower surface 100 b of the substrate 100. A plurality of contact holes 704 are formed at the bottom of the trench 702. The contact hole 704 exposes the conducting pad structure 110 under the substrate 100. The conducting layer 114 may extend to the conducting pad structure along the upper surface 100 a of the substrate 100, the sidewall of the trench 702, and the sidewall of the contact hole 704, and the conducting pad structure 110 may be similar to the embodiments mentioned above and include a plurality of conducting pads having specifically designed patterns. The conducting layer 114 may extend along the sidewalls of the formed holes to electrically contact with the conducting pads. In addition, in this embodiment, the substrate 100 may include a transparent substrate 106 b and a spacer layer 106 a disposed thereon. The spacer layer 106 a, the substrate 100, and the transparent substrate 106 b may surround a cavity. A chip 700 may be disposed in the cavity, which may be, for example, (but is not limited to) a light sensing chip or a light emitting chip.

In a chip package according to embodiments of the invention, each pattern of the multi-layered conducting pads is designed such that a through-substrate conducting structure formed in the package may electrically contact with the multi-layered conducting pads, improving the structural reliability of the chip package and increasing conducting routes connected to the through-substrate conducting structure.

FIGS. 8-13 are cross-sectional views showing the steps of forming a chip package according to an embodiment of the present invention. As shown in FIG. 8, a wafer 1 is provided, which includes a plurality of chips 3 such as a CMOS image sensor chip. The chip includes a substrate 5, wherein an active region 10A and peripheral circuit regions 10B are defined. The chip 3 has a front surface 100 a and a back surface 100 b. An image sensor device 7 and a conducting pad structure 9 are disposed on the front surface 100 a in the active region 10A and the peripheral circuit region 10B, respectively. The substrate 5 includes, for example, a semiconductor material or a ceramic material. In one embodiment, the substrate 5 is a semiconductor wafer (such as a silicon wafer) which is suitable for a wafer-level packaging process. Adopting a wafer-level packaging process to form chip packages may reduce fabrication cost and fabrication time.

In one embodiment, the conducting pad structure 9 may be constructed by a metal layer or a stacked structure composed by a plurality of conducting pads such as a plurality of conducting pads having a dielectric layer 11 interposed therebetween. The detailed structure of the conducting pad structure 9 will be illustrated in company with the following embodiments. Typically, a chip passivation layer 13, such as an oxide layer, nitride layer, or composite layer, is covered on the front surface of the chip. An opening may be optionally formed in the chip passivation layer 13 on the position above the conducting pad structure, depending on the packaging process type.

Referring to FIG. 9, in one embodiment the front surface 100A of the wafer 1 is bonded to a carrier wafer 17 to form a bonding surface, wherein the wafer 1 and the carrier wafer may be bonded together through a bonding layer 15, depending on the bonding techniques. Thus, in one embodiment, the bonding surface between the conducting pad structure 9 on the front surface 100A and the carrier wafer 17 includes an intermediate layer 19 such as the chip passivation layer 13 and/or the bonding layer 15. A thinning process may be next applied to the back surface 100B of the wafer 1 such that light can enter the image sensing region from the back surface.

Referring to FIG. 10, in the next process step, another carrier wafer 23 is attached on the back surface 100B of the substrate 5 of the wafer, which may be, for example, a wafer composed of a transparent material such as glass. A spacer layer 21 may be formed between the substrate 5 and the carrier wafer 23. In one embodiment, a cavity may be formed on the active region of the substrate 5 and between the carrier wafer 23 and the spacer layer 21. Another thinning process may be performed to reduce a thickness of the carrier wafer 17.

Referring to FIG. 11, a through hole 25 is subsequently formed in locations in the carrier wafer corresponding to the conducting pad structures. In this embodiment, the through hole is chosen to be formed with a conical or pyramidical profile with a steep sidewall, wherein the angle θ is between about 90° and 92°. Then, an insulating layer 27, such as an oxide layer, a light sensitive insulating layer, or a photoresist is conformally formed such that the insulating layer extends from the carrier wafer 17 to an inner sidewall and a bottom of the through hole 25.

Referring to FIG. 12, a process step where the conducting pad structure 9 is exposed is performed to form an opening 30 at the bottom of the through hole 25. In this embodiment, the opening may penetrate a bonding surface, such as the intermediate layer 19, between two wafers. The depth of the opening may stop at an upper surface of the conducting pad structure and/or partially penetrate the conducting pad to reach the dielectric layer 11. Alternatively, the depth of the opening may further partially or completely penetrate the substrate 5 and stop at the spacer layer 21. The process steps and the structure mentioned above will be illustrated in detail in the following description.

Referring to FIG. 13, a conducting layer 32 formed of, for example, a metal material is conformally formed on the surface of the carrier wafer 17. The conducting layer extends into the sidewall and the bottom of the through hole and the opening 30 to contact the conducting pad structure to form a conducting route. Then, a passivation layer 34 formed of, for example, a solder mask material is filled therein. Then, external connecting elements such as pads electrically connecting to the conducting layer 32 are fabricated and a wafer dicing process is performed to finish the fabrication of the chip package (not shown).

In another embodiment, as shown in FIGS. 14A and 14B, a cross-sectional view and a top view of another through hole structure are shown. In this embodiment, a process step such as an etching process is performed to the surface of the carrier wafer 17 to remove a portion of the material of the substrate such that a trench T having a predetermined depth D is formed. In the case that the carrier wafer 17 is a blank wafer, because no circuit element is formed therein, the opening, the location, or the depth of the trench T has more variations. The trench T may be formed on a location including a scribe line SC. Meanwhile, the range of the trench T may correspond to a plurality of conducting pad structures 9. For example, the range of the trench includes a whole sideline region. Then, a process step such as an etching process is performed to the bottom of the trench to remove a portion of the substrate material to form a plurality of through holes H each having a predetermined depth D1. Note that because the trench T can significantly reduce an aspect ratio of the through hole H, the difficulty of the process step of forming the opening 30 at the bottom of the through hole H can be reduced.

Hereafter, the manufacturing process of the opening 30 and the stacked structure of the conducting pad structures 9 (multilayer conducting pads) are illustrated.

Referring to FIG. 15A, an enlarged cross-sectional view showing the area of the opening 30 and the conducting pad 9 of the embodiment shown in FIG. 12 or FIG. 14A is shown. Multilayer conducting pads 9A and 9B, interlayer dielectric layers 11, and a bonding surface such as an intermediate layer 19 are formed on the substrate 5. In one embodiment, a pattern of the upper conducting pad 9A is designed such that a portion of the lower conducting pad 9B is exposed. In one embodiment, the upper conducting pad 9A has at least an insulating window 36. The insulating window 36 corresponds to the conducting pad 9B directly thereunder. That is, an opening, a recess, or a trench is simultaneously defined during the fabrication process of the upper conducting pad 9A, which is filled with the interlayer dielectric layer 11. In this embodiment, the insulating window 36 overlaps with a portion of the lower conducting pad 9B. The insulating window 36 is formed before the formation of the through hole or the bonding of the carrier wafer 17.

Then, with reference made to FIG. 14A, after the through hole H and the insulating layer 27 are formed in the substrate of the carrier wafer 17, a portion of the insulating layer 27 on the bottom of the through hole H is removed to form the opening 30, wherein this process step may be simultaneously or successively performed with the following process step. As shown in FIG. 15B, the process step includes removing the intermediate layer 19 to form the insulating window 36, and a portion of the interlayer dielectric layer 11 to expose a sidewall of the upper conducting pad 9A and a surface of the lower conducting pad 9B. For example, a suitable etching process including a photolithography process and an etching process may be chosen to accomplish the fabrication process mentioned above since the etching selectivity for the insulating layer and the metal are different.

Then, as shown in FIG. 15C, the conducting layer 32 is formed to electrically connect one or multiple layers of the conducting pad structure. For example, the conducting pad 32 may simultaneously contact with the sidewall of the upper conducting pad and/or the upper surface of the lower conducting pad.

Referring to FIGS. 16A-16C, cross-sectional views showing the steps of forming a stacked structure of three conducting pads are illustrated, which includes an upper conducting pad 9A on an insulating window 36A, an intermediate conducting pad 9B having an insulating window 36B, and a lower conducting pad 9C, wherein the insulating window 36A is larger than the insulating window 36B, and both the two insulating windows correspond to an upper surface of the lower conducting pad 9C. In this embodiment, as shown in FIG. 16C, the formed conducting layer 32 may be electrically connected to one or multiple layers of the conducting pad structure. For example, the conducting layer 32 may simultaneously contact with a sidewall of the upper conducting pad 9A, an upper surface and a sidewall of the intermediate conducting pad 9B, and/or an upper surface of the lower conducting pad 9C.

Next, referring to FIGS. 17A-17C, cross-sectional views showing the steps of forming a stacked structure of three conducting pads are illustrated. The difference between the embodiment and the embodiment mentioned above is that the lower conducting pad 9C also includes an insulating window 36C which has a corresponding relationship with the insulating window 36A of the upper conducting pad 9A and the insulating window 36B of the intermediate conducting pad 9B. Note that the insulating window 36C of the lower conducting pad 9C is smaller than the insulating windows 36A and 36B.

The step of forming the opening 30 includes removing the intermediate layer 19, the insulating windows 36A, 36B, and 36C, and a portion of the interlayer dielectric layer 11 to expose the sidewalls and a portion of the upper surface of the multilayer conducting pads. For example, a suitable etching process including a photolithography process and an etching process may be chosen to accomplish the fabrication process mentioned above since the selectivity for the insulating layer and the metal are different. Therefore, a contact area between the subsequently formed conducting layer 32 and the stacked structure of the conducting pads may be increased and the conducting layer 32 may be conformally formed.

According to required characteristics, the spacer layer 21 may also be chosen as a blocking layer. A portion of the silicon substrate 5 is further removed to form an opening 30A. The opening 30A may be located in the silicon substrate 5 or expose the spacer layer 21. Then, as shown in FIG. 17C, a conducting layer 32 is formed to electrically connect to one layer or multiple layers of the conducting pad structure. Alternatively, the conducting layer may simultaneously contact with a sidewall and/or an upper surface of the conducting pad. The conducting layer 32 may extend from the opening 30A to the silicon substrate 5. In one embodiment, before the conducting layer 32 is formed, another insulating layer 38 may be formed in the opening 30A. Alternatively, an oxidation process may be performed to form an oxide layer on the silicon substrate 5 in the opening 30A.

While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements. 

What is claimed is:
 1. A chip package, comprising: a substrate having an upper surface and a lower surface; a plurality of conducting pads in a stacked structure, comprising at least an upper conducting pad above a lower conducting pad, wherein the upper conducting pad is located under the lower surface of the substrate, wherein the upper conducting pad of the conducting pads has at least an opening or a trench exposing the lower conducting pad of the conducting pads; a dielectric layer located between adjacent conducting pads; a hole extending from the upper surface towards the lower surface of the substrate, wherein a sidewall or a bottom of the hole exposes a portion of the conducting pads, and an upper opening of the hole near the upper surface is smaller than a lower opening of the hole near the lower surface, wherein a thickness of at least one of the conducting pads near the hole increases along a direction away from the hole; and a conducting layer located in the hole and electrically contacting at least one of the conducting pads.
 2. The chip package as claimed in claim 1, wherein the bottom of the hole exposes an upper surface of at least one of the conducting pads.
 3. The chip package as claimed in claim 1, wherein the sidewall of the hole exposes a side of at least one of the conducting pads.
 4. A chip package, comprising: a substrate having an upper surface and a lower surface; a plurality of conducting pads in a stacked structure, comprising at least an upper conducting pad above a lower conducting pad, wherein the upper conducting pad is located under the lower surface of the substrate; a dielectric layer located between adjacent conducting pads; a hole extending from the upper surface towards the lower surface of the substrate, wherein a sidewall or a bottom of the hole exposes a portion of the conducting pads, and an upper opening of the hole near the upper surface is smaller than a lower opening of the hole near the lower surface, wherein a thickness of at least one of the conducting pads near the hole increases along a direction away from the hole; a conducting layer located in the hole and electrically contacting at least one of the conducting pads; and a trench extending from the upper surface towards the lower surface of the substrate, wherein the trench is located on the hole, a bottom of the trench comprises a plurality of contact holes, and one of the contact holes is the hole.
 5. The chip package as claimed in claim 1, further comprising a spacer layer disposed under the conducting pads, wherein the hole further extends into the spacer layer.
 6. The chip package as claimed in claim 5, further comprising a transparent substrate disposed under the lower surface of the substrate, and the spacer layer is located between the substrate and the transparent substrate.
 7. The chip package as claimed in claim 6, further comprising an image sensor device located between the transparent substrate and the upper surface of the substrate.
 8. The chip package as claimed in claim 1, further comprising a second substrate located under the lower surface of the substrate and the conducting pads.
 9. The chip package as claimed in claim 8, further comprising an image sensor device located in the second substrate.
 10. The chip package as claimed in claim 8, wherein the hole further extends into the second substrate.
 11. The chip package as claimed in claim 10, further comprising an insulating layer located between the conducting layer and the second substrate.
 12. The chip package as claimed in claim 8, further comprising a spacer layer disposed under the conducting pads, wherein the hole further extends into the spacer layer.
 13. The chip package as claimed in claim 12, further comprising an insulating layer located between the conducting layer and the second substrate and located between the conducting layer and the spacer layer.
 14. The chip package as claimed in claim 10, further comprising a transparent substrate disposed under the lower surface of the substrate, and the spacer layer is located between the substrate and the transparent substrate.
 15. The chip package as claimed in claim 8, further comprising a trench extending from the upper surface towards the lower surface of the substrate, wherein the trench is located on the hole, a bottom of the trench comprises a plurality of contact holes, and one of the contact holes is the hole.
 16. The chip package as claimed in claim 1, wherein the conducting pads are a stacked structure comprising at least an upper conducting pad and a lower conducting pad, wherein the upper conducting pad has a window larger than a window of the lower conducting pad.
 17. A chip package, comprising: a substrate having an upper surface and a lower surface, wherein the substrate is a semiconductor substrate; a plurality of conducting pads in a stacked structure, comprising at least an upper conducting pad above a lower conducting pad, wherein the upper conducting pad is located under the lower surface of the substrate; a dielectric layer located between adjacent conducting pads; a hole extending from the upper surface towards the lower surface of the substrate, wherein a sidewall or a bottom of the hole exposes a portion of the conducting pads, and an upper opening of the hole near the upper surface is smaller than a lower opening of the hole near the lower surface, wherein a thickness of at least one of the conducting pads near the hole increases along a direction away from the hole; and a conducting layer located in the hole and electrically contacting at least one of the conducting pads. 